Towards Parallel VHDL Simulation

In hardware design of today, there is a growing usage of hardware design languages to speed up the time-to-market. As the design complexity grows, so does the simulation time. To solve this problem, several research groups have suggested the use of parallel computers to speed up simulation. This report surveys some of the issues involved when designing a parallel simulator for one of the more popular hardware description languages, VHDL. The report includes a brief survey of VHDL itself, as well as a survey of simulation methodologies, especially parallel discrete event simulation. Some important issues when designing a parallel VHDL simulator are addressed and some parallel VHDL simulation projects and experiments that already have been initiated are described briefly. The report concludes with some general remarks on important research that needs to be done as well as suggesting a suitable approach for future research.